Double mask hermetic passivation method providing enhanced resis

Details Double mask hermetic passivation method providing enhanced resis Double mask hermetic passivation method providing enhanced resis

1996-12-31

1998-04-07

Tsai, Jey

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Rendering selected devices operable or inoperable

438132, H01L 2170

Patent

active

057364338

ABSTRACT:
A passivation structure is formed using two passivation layers and a protective overcoat layer using two masking steps. The first passivation layer is formed over the wafer and openings are provided to expose portions of the pads for testing the device and fusible links. After testing and laser repair, a second passivation layer is formed over the wafer followed a deposit of the protective overcoat. The protective overcoat is patterned and etched, exposing the pads. The remaining portions of the protective overcoat are used as a mask to remove portions of the second passivation layer overlying the pads. Leads are then attached to pads and the devices are encapsulated for packaging. The second passivation layer overlaps edge portions of the first passivation layer at the bond pads to enhance moisture resistance.

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IBM Technical Disclosure Bulletin, vol. 20, No. 8, Jan. 1978, NY, U.S., pp. 3189-3190, H. Remshardt et al., "Tolerance Trimming of Electrical Data of LSI Semiconductor Circuits".

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