Wiring structure for semiconductor integrated circuit device

Details Wiring structure for semiconductor integrated circuit device Wiring structure for semiconductor integrated circuit device

1988-10-06

1990-07-24

LaRoche, Eugene R.

357 68, 357 71, H01L 2710, H01L 2715, H01L 2348, H01L 2954

Patent

active

049438417

ABSTRACT:
A wiring structure for a semiconductor integrated circuit device having a common wiring region such as a gate array comprises a lower wiring layer formed on a semiconductor substrate with a predetermined lattice form and an upper wiring layer formed on an insulating film on the lower layer with a lattice form orthogonal to the lower lattice. The wiring lattice of the lower wiring layer is cut at intermediate portions thereof between the wiring lattices of the upper wiring layer into segments, ends of the segments being exposed through through-holes perforated in the insulating film in portion thereof except crossing points of the upper and lower wiring lattices. Predetermined through-holes are buried with a connecting wiring having a predetermined pattern at the time of forming the wiring lattice of the upper wiring layer to connect the upper layer to the lower layer and are buried with discretely provided connecting wirings to connect the segments to each other. Since the wiring structure can be formed by the single step wiring processing to a semicustomized LSI having a common region such as gate array, the number of photomasks is minimized for customization of the semicustomized LSI.

REFERENCES:
patent: 4568961 (1986-02-01), Noto
patent: 4673966 (1987-06-01), Shimoyama
patent: 4689654 (1987-08-01), Brockmann
patent: 4689657 (1987-08-01), Percival et al.
patent: 4716308 (1987-12-01), Matsuo et al.
patent: 4825273 (1989-04-01), Arakawa
Balyoz et al., "Densified Wiring Channels Design Concept", IBM Technical Disclosure Bulletin, vol. 17, No. 7, Dec. 1974, pp. 1958-1959.

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