Methods and apparatus for subtraction with 3:2 carry-save adders

Details Methods and apparatus for subtraction with 3:2 carry-save adders Methods and apparatus for subtraction with 3:2 carry-save adders

1992-08-31

1994-09-27

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

053512073

ABSTRACT:
A hardware logic arrangement for subtraction using a 3:2 carry-save-adder (CSA) for use with high speed floating point computation circuits. Three operands to be combined are routed to the three inputs of the CSA via separate multiplexors (MUXs) and appropriate inverting logic. Output sum and carry vectors are routed via further MUXs to separate latch storage registers. Subtraction executed as addition of the inverse of an operand is implemented by routing a constant "1" to the MUX steering the output carry vector to its associated latch.

REFERENCES:
patent: 3976866 (1976-08-01), Motegi et al.
patent: 4110832 (1978-08-01), Leininger et al.
patent: 4888723 (1984-12-01), Man et al.
Computer Arithmetic, Principles, Architecture, and Design, pp. 98-102, John Wiley & Sons, 1979, Hwang.

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