Semiconductor inversion layer transistor

Details Semiconductor inversion layer transistor Semiconductor inversion layer transistor

1980-03-26

1982-04-20

Edlow, Martin H.

357 16, 357 89, H01L 29161

Patent

active

043262082

ABSTRACT:
A semiconductor inversion layer transistor which is compatible with semiconductor fabrication technology, and an integrated circuit which incorporates a plurality of such transistors. In one embodiment of the transistor, a P type indium arsenide base and a P type gallium antimonide emitter are used while the collector can be made of either P type gallium antimonide or N type indium arsenide. By the nature of the band alignment at the interface, the indium arsenide base has its Fermi level pinned in the conduction ban at the base-emitter junction and an assymetrically conducting charge barrier which is formed at this junction is preferential to injection of carriers flowing from the emitter to the base rather than vice versa. When the base-emitter junction is forward biased the electrons at the junction are projected across the base with minimal hole injection from base to emitter, thus providing a high gain transistor having excellent high frequency characteristics.

REFERENCES:
patent: 3209215 (1965-09-01), Esaki
Chang et al., I.B.M. Tech. Discl. Bull., pp. 1689-1690, Sep. 1978.
Chang et al., Appl. Phys. Lett., 35(12)15, Dec. 1979, pp. 939-942.
Chang et al., I.B.M. Tech. Discl. Bull., vol. 21, No. 11, Apr. 1979, p. 4692.

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