Synchronous semiconductor memory device

Details Synchronous semiconductor memory device Synchronous semiconductor memory device

1999-07-29

2000-11-21

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36523003, G11C 800

Patent

active

061512737

ABSTRACT:
A synchronous semiconductor memory device capable of improving substantial transfer rate is provided. In response to a write command immediately following an act command, a control signal generating circuit applies an inactive enable signal to a read preamplifier & write buffer. In response to a write command and a precharge command, the control signal generating circuit generates an active enable signal, and the read preamplifier & write buffer writes the data stored in an FIFO to a memory cell. As late write is not performed upon reception of a write command immediately following an act command, erroneous writing of data to a not intended address can be prevented.

REFERENCES:
patent: 5515325 (1996-05-01), Wada
patent: 5517462 (1996-05-01), Iwamoto et al.

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