Static information storage and retrieval – Addressing – Sync/clocking
Patent
1999-07-16
2000-11-21
Nelms, David
Static information storage and retrieval
Addressing
Sync/clocking
365191, G11C 800
Patent
active
061512729
ABSTRACT:
Integrated circuit memory devices that utilize preferred masking techniques include a memory cell array and a mask signal generator that generates first and second internal data masking signals in response to at least one single data rate mode signal. A data controller is also provided to pass input write data to the memory cell array when the first and second internal data masking signals are inactive and mask at least a portion of the input write data from the memory cell array when one of the first and second internal data masking signals is active. This ability to mask data facilitates operation of the memory device in a specialized single data rate mode for testing using conventional test equipment.
REFERENCES:
patent: 5521878 (1996-05-01), Ohtani et al.
La One-gyun
Lee Jung-bae
Lee Si-Yeol
Nelms David
Samsung Electronic Co. Ltd.
Tran M.
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