Non-volatile semiconductor memory device and data erase method o

Details Non-volatile semiconductor memory device and data erase method o Non-volatile semiconductor memory device and data erase method o

1998-12-28

2000-11-21

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518514, 36518524, G11C 1604

Patent

active

061512540

ABSTRACT:
A non-volatile semiconductor memory device capable of reducing the erase voltage which is generated by a booster circuit and used for erasion of data stored therein is disclosed. The non-volatile semiconductor memory device comprises a memory cell array composed of a plurality of memory cells each having a control gate connected to a word line, a floating gate to which data is written and an erase gate for erasing the data of said floating gate on the basis of a first voltage applied thereto, a word decoder for selecting the word line, an erase gate decoder for selecting the erase gate and voltage applying means for generating the first voltage and applying the first voltage to the erase gates of the memory cells when the erase gate decoder outputs a second voltage lower than the first voltage to the erase gates of the memory cells. When the second voltage applied to the erase gate is held and a voltage based on the capacitance between the control gate and the erase gate is added to the second voltage when a predetermined voltage is applied from the word decoder through a word line to the erase gate and a resultant voltage is applied as the first voltage. Further, the capacitance between the erase gate and the floating gate is made sufficiently smaller than the capacitance between the erase gate and the control gate.

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