Frequency divider arrangement

Details Frequency divider arrangement Frequency divider arrangement

1980-01-21

1982-02-09

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

328 37, 328 46, 364703, H03K 2136

Patent

active

043151663

ABSTRACT:
A high frequency divider arrangement for use in transmission systems operating in the gigabit/second range. Known divider arrangements based on ECL logic families have an upper frequency limit which is too low for dividing signals in the gigabit/second range. In one embodiment the inputs of a high frequency multiplexer are connected respectively to the stages of a feedback shift register which produces a sequence of five code words which are serialized by a multiplexer. The bits in the serialized code words occur in blocks which define a mark/space ratio of the output signal which has a frequency of 2/5ths of the clock frequency applied to the multiplexer. By means of additional circuitry, for example D-type flip-flops, the output from the multiplexer can be divided further. The code word(s) applied to the multiplexer can be held static, changed each time the inputs of the multiplexer have been scanned, or held temporarily static for a predetermined number of scans and then changed.

REFERENCES:
patent: 3375449 (1968-03-01), Ribour et al.
patent: 3460129 (1969-08-01), Thorvaldsson
patent: 3818354 (1974-06-01), Tomisawa et al.
patent: 3970941 (1976-07-01), Leuschner
patent: 4234849 (1980-11-01), Crilly

Affiliated with

Also associated with

Rating

Frequency divider arrangement does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Frequency divider arrangement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Frequency divider arrangement will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1262235