Serial to parallel converter enabled by multiplexed flip-flop co

Coded data generation or conversion – Digital code to digital code converters – Parallel to serial

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341141, H03M 900, H03M 100

Patent

active

061509655

ABSTRACT:
A parallel to serial converter comprising a parallel word latch for receiving a series of words comprised of parallel data words, a shift register for receiving the parallel data words and for storing bits of a parallel data word in a series of shift register stages upon receipt of a first enable signal, and for providing a serial stream of bits at a serial clock rate, a circuit for receiving a serial clock signal and for providing the serial clock signal to the shift register to enable shifting of the stored bits to an output as the serial stream of bits, and a controller for generating the enable signal and for applying the enable signal to the shift register and parallel word latch, said controller being comprised of a counter for counting input clock pulses at a serial bit rate and for providing the enable signal upon counting plural input clock pulses, the counter being comprised of active elements restricted to plural combination multiplexed flip/flops.

REFERENCES:
patent: 5686913 (1997-11-01), Coln et al.

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