Processor configured to generate lookahead results from operand

Details Processor configured to generate lookahead results from operand Processor configured to generate lookahead results from operand

1998-07-14

2000-08-29

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

712217, 712218, C06F 938

Patent

active

061122939

ABSTRACT:
A processor includes a lookahead address/result calculation unit which is configured to receive operand information (either the operand or a tag identifying the instruction which will produce the operand value) corresponding to the source operands of one or more instructions. If the operands are available, lookahead address/result calculation unit may generate either a lookahead address for a memory operand of the instruction or a lookahead result corresponding to a functional instruction operation of the instruction. The lookahead address may be provided to a load/store unit for early initiation of a memory operation corresponding to the instruction. The lookahead result may be provided to a speculative operand source (e.g. a future file) for updating therein. A lookahead state for a register may thereby be provided early in the pipeline. Subsequent instructions may receive the lookahead state and use the lookahead state to generate additional lookahead state early. On the other hand, the subsequent instructions may receive the lookahead state and hence may be prepared for execution upon dispatch to an instruction window (as opposed to waiting in the instruction window for execution of the prior instruction). In one embodiment, the processor also includes an operand collapse unit configured to collapse the lookahead results into subsequent, concurrently decoded instructions (intraline dependencies). Additionally, the operand collapse unit may be configured to collapse a compare instruction into a subsequent branch instruction which depends upon the result of the compare.

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