Patent
1997-12-18
2000-08-29
Harrell, Robert B.
G06F 1200
Patent
active
061120189
ABSTRACT:
A floating point unit capable of executing multiple instructions in a single clock cycle using a central window and a register map is disclosed. The floating point unit comprises: a plurality of translation units, a future file, a central window, a plurality of functional units, a result queue, and a plurality of physical registers. The floating point unit receives speculative instructions, decodes them, and then stores them in the central window. Speculative top of stack values are generated for each instruction during decoding. Top of stack relative operands are computed to physical registers using a register map. Register stack exchange operations are performed during decoding. Instructions are then stored in the central window, which selects the oldest stored instructions to be issued to each functional pipeline and issues them. Conversion units convert the instruction's operands to an internal format, and normalization units detect and normalize any denormal operands. Finally, the functional pipelines execute the instructions.
REFERENCES:
patent: 4044338 (1977-08-01), Wolf
patent: 4453212 (1984-06-01), Gaither et al.
patent: 4807115 (1989-02-01), Torng
patent: 4835738 (1989-05-01), Niehaus et al.
patent: 4858105 (1989-08-01), Kuriyama et al.
patent: 4928223 (1990-05-01), Dao et al.
patent: 5001629 (1991-03-01), Murakami et al.
patent: 5053631 (1991-10-01), Perlman et al.
patent: 5058048 (1991-10-01), Gupta et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5136697 (1992-08-01), Johnson
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226130 (1993-07-01), Favor et al.
patent: 5367650 (1994-11-01), Sharangpani et al.
patent: 5634046 (1997-05-01), Chatterjee et al.
patent: 5634118 (1997-05-01), Blomgren
patent: 5640582 (1997-06-01), Hays et al.
patent: 5651125 (1997-07-01), Witt et al.
patent: 5696955 (1997-12-01), Goddard et al.
patent: 5727176 (1998-03-01), Clift et al.
patent: 5771366 (1998-06-01), Bjorksten et al.
Intel, "Chapter 2: Microprocessor Architecture Overview," 1994, pp. 2-1 through 2-4.
Michael Slater, "AMD's K5 Designed to Outrun Pentium," Microprocessor Report, vol. 8, No. 14, Oct. 24, 1994, 7 pages.
Sebastian Rupley and John Clyman, "P6: The Next Step?," PC Magazine, Sep. 12, 1995, 16 pages.
Tom R. Halfhill, "AMD K6 Takes On Intel P6," BYTE, Jan. 1996, 4 pages.
"Intel Architecture Software Developer's Manual, vol. 1: Basic Architecture", Intel Corporation, Prospect IL, 1996, 1997, Chapter 8: Programming With The Intel MMX.TM. Technology, pp 8-1 through 8-15.
Holstad, S., "Tutorial Tuesday: Decoding MMX" Jan. 14, 1997, Earthlink Network, Inc. copyright 1997, 5 pages (see http://www.earthlink.net/daily/Tuesday/MMX).
"Intel MMX.TM. Technology--Frequently Asked Questions" 6 pages (see http://www.intel.com/drg/mmx/support/faq/htm).
Meyer Derrick R.
Tran Thang M.
Advanced Micro Devices , Inc.
Christen Dan R.
Harrell Robert B.
Kivlin B. Noel
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