Boots – shoes – and leggings
Patent
1990-04-09
1994-06-14
Kulik, Paul V.
Boots, shoes, and leggings
395425, 364DIG1, 364243, 3642434, 36424341, 3642563, 3642564, 3642565, G06F 1210
Patent
active
053218361
ABSTRACT:
Microprocessor architecture for an address translation unit which provides two levels of memory management is described. Segmentation registers and an associated segmentation table in main memory provide a first level of memory management which includes attribute bits used for protection, priority, etc. A page cache memory and an associated page directory and page table in main memory provide a second level of management with independent protection on a page level.
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Crawford John H.
Ries Paul S.
Intel Corporation
Kulik Paul V.
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