Reconfigurable, fault tolerant, multistage interconnect network

Details Reconfigurable, fault tolerant, multistage interconnect network Reconfigurable, fault tolerant, multistage interconnect network

1991-05-01

1994-06-14

Richardson, Robert L.

Multiplex communications

Wide area network

Packet switching

370 60, 370 941, G06F 1300

Patent

active

053218132

ABSTRACT:
A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 log.sub.b N stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and log.sub.b N indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.

REFERENCES:
patent: 4829227 (1989-05-01), Turner
patent: 4962497 (1990-10-01), Ferenc et al.
patent: 5119370 (1992-06-01), Terry
Leiserson-IEEE Transactions on Computers-vol. C-34, No. 10, Oct. 1985.
Final Report--Numerical Aerodynamic Simulation Facility--Burroughs Corp. Mar. 1979.

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