Memory LSI with arithmetic logic processing capability, main mem

Details Memory LSI with arithmetic logic processing capability, main mem Memory LSI with arithmetic logic processing capability, main mem

1997-07-21

1999-01-19

Pan, Daniel H.

39580036, 395894, 39518201, G06F 1116, G06F 1316

Patent

active

058623965

ABSTRACT:
In a main memory with arithmetic logic processing capability, k first memories (k is an integer equal to or more than 0) are connected to a memory bus, for storing data. M second memories with arithmetic logic processing capability (m is an integer equal to or more than 1) are also connected to the memory bus. Each of the m second memories includes a memory section for storing data, and an arithmetic logic processing section. The arithmetic logic processing section performs a first processing to at least a part of the data stored in the memory section in response to a first instruction inputted via the memory bus, and allows a result of the first processing to be outputted onto the memory bus in response to a second instruction inputted via the memory bus. The arithmetic logic processing section may further includes a macro code RAM for storing macro codes. The main memory with arithmetic logic processing capability and a memory device with arithmetic logic processing capability used in the same have compatibility with a corresponding main memory and a corresponding memory device.

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