Method and apparatus for a minimal memory in-circuit digital tes

Details Method and apparatus for a minimal memory in-circuit digital tes Method and apparatus for a minimal memory in-circuit digital tes

1990-12-06

1994-06-14

Beausoliel, Jr., Robert W.

Excavating

371 221, 371 225, G06F 1100, G01R 3128

Patent

active

053217012

ABSTRACT:
A minimal memory in-circuit digital tester with vector memory concentrated in a centralized vector processor circuit, eliminating the need for pin memory. The vector processor circuit memory is partitioned into two blocks, a pointer memory and a change list memory. Every vector clock cycle has one pointer memory entry. The pointer memory entry is an address for the change list memory. The change list memory contains lists of nodes used in the vector test sequence. Each change list entry contains a pin number and several control bits. The control bits define functions such as whether the pin will toggle its data or enable state, whether there are more pins in that particular change list, and whether the list or test has ended. When the end of each change list is reached, all pins that have been primed by that change list will be toggled. The next entry of the pointer memory is then selected which, in turn, selects another, or perhaps the same change list in the change list memory. Each vector within a test vector file corresponds to one entry in the pointer memory, however, several different pointers can address the same change list. As a result, test vector files of great length can be accommodated using minimal memory.

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