Information device for providing fast data transfer with minimum

Details Information device for providing fast data transfer with minimum Information device for providing fast data transfer with minimum

1995-03-03

1996-10-15

Treat, William M.

395846, G06F 1338

Patent

active

055663508

ABSTRACT:
An information device which ensures fast data transfer between a RAM and an I/O channel, between an I/O channel and another I/O channel, or between a RAM and another RAM: comprises address decoder circuit which allows the CPU to gain simultaneous access to both the RAM and the I/O channel when the CPU accesses a data transfer area mapped for data transfer, and an inverter which assures that both the RAM and the I/O channel operate in a mutually opposite manner, either in one mode in which the RAM works in a read operation with the I/O channel in a write operation or vice versa in response to the access request of read/write from the CPU. By assuring that both the RAM and the I/O channel operate in a mutually opposite manner, in response to an access from the CPU, data transfer between the RAM and the I/O channel is completed in a single access from the CPU; thus, fast data transfer is achieved.

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Sayers et al. "Principles of Microprocessors". 1991. pp. 177-182.

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