Method and apparatus for state machine optimization using device

Details Method and apparatus for state machine optimization using device Method and apparatus for state machine optimization using device

1996-09-03

1999-01-19

Oberley, Alvin E.

G06F 104

Patent

active

058623698

ABSTRACT:
A method and apparatus which enables circuitry to detect and take advantage of the intrinsic performance or delay characteristic of the respective device in which the circuitry is embedded. By determining the delay characteristics of the device and sampling signals based on this information, the circuitry may not be required to wait for additional clock cycles which is required for logic in prior art devices which do not take advantage of the device's intrinsic performance. This considerably increases device performance. A device delay encoder circuit included in a device encodes the instantaneous delay coefficient of the device in question and a clocking signal is used to determine whether the delay elements should be considered fast or slow. All of the logic circuitry on a chip have a similar derating factor, and thus the performance of the delay elements is indicative of the performance of the entire chip. The encoded device delay information is then used by logic circuitry in the respective device on that cycle to determine when to sample Therefore, where a respective device has a small delay coefficient, and the device includes logic according to the present invention, the device can perform operations in a reduced number of clock cycles. This significantly increases device performance.

REFERENCES:
patent: 4079456 (1978-03-01), Lunsford et al.
patent: 4482863 (1984-11-01), Auston et al.
patent: 4559636 (1985-12-01), Goldrian
patent: 4641246 (1987-02-01), Halbert et al.
patent: 4807147 (1989-02-01), Halbert et al.
patent: 4851998 (1989-07-01), Hospodor
patent: 4979177 (1990-12-01), Jackson
patent: 5138320 (1992-08-01), Ngo et al.
patent: 5180937 (1993-01-01), Laird et al.
patent: 5228066 (1993-07-01), Devane
patent: 5245231 (1993-09-01), Kocis et al.
patent: 5253352 (1993-10-01), Olson
patent: 5268656 (1993-12-01), Muscavage
patent: 5272390 (1993-12-01), Watson et al.
patent: 5272729 (1993-12-01), Bechade et al.
patent: 5282213 (1994-01-01), Leigh et al.
patent: 5572715 (1996-11-01), Gowni
Cox et al. "VLSI performance compensation for off-chip drivers and clock generation", Proceedings of the IEEE 1989 Custom Integrated Circuits Conference (Cat. No. 89Ch2671-6), p. 14.3/1-4, May 18, 1989.

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