Memory management device

Details Memory management device Memory management device

1990-05-18

1992-04-28

Fleming, Michael R.

Boots, shoes, and leggings

3642426, 36424292, 3642423, G06F 1336

Patent

active

051094916

ABSTRACT:
A memory management device which is connected in a virtual address space or a physical address space together with another device capable of becoming a bus master, is endowed with the function of detecting the bus request signal of the other device, interrupting an address translation process under execution and causing a processor to release a bus. Thus, the other device can be made the bus master without being kept waiting for a long time, and a system bug can be prevented which is attributed to such a fact that a wait time exceeds the data hold time of an input/output device connected to, for example, a direct memory access controller.

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patent: 4417304 (1983-11-01), Dinwiddie, Jr.
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patent: 4558412 (1985-12-01), Inoshita et al.
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patent: 4648029 (1987-03-01), Cooper et al.
patent: 4669043 (1987-05-01), Kaplinsky
patent: 4805097 (1989-02-01), De Sanna
Nikkei Electronics, Dec. 5, 1983, Nikkei McGraw-Hill Inc., pp. 146-150 (English translation enclosed).

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