Analog neural nets supplied digital synapse signals on a bit-sli

Details Analog neural nets supplied digital synapse signals on a bit-sli Analog neural nets supplied digital synapse signals on a bit-sli

1990-08-01

1992-08-18

Fleming, Michael R.

Boots, shoes, and leggings

364602, 395 27, G06F 1518

Patent

active

051405318

ABSTRACT:
Plural-bit digital input signals to be subjected to weighted summation in a neural net layer are bit-sliced; and a number N of respective first through N.sup.th weighted summations of the bits of the digital input signals in each bit slice are performed, resulting in a respective set of first through N.sup.th partial weighted summation results. Weighted summations of the partial weighted summation results of similar ordinal number are then performed to generate first through N.sup.th final weighted summation results. Each weighted summation of a bit slice of the digital input signals is performed using a capacitive network that generates partial weighted summation results in the analog regime. In this capacitive network each weight is determined by the difference in the capacitances of a respective pair of capacitive elements. The weighted summation to generate a final weighted summation result also is advantageously done in the analog regime, since this facilitates the analog final weighted summation result being non-linearly processed in an analog amplifier with sigmoidal response. This non-linear processing generates an analog axonal output response for a neural net layer, which analog axonal output response can then be digitized.

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Bloomer et al., "A Preprogrammed Artificial Neural Network Architecture in Signal Processing", Proceedings IEEE 1990 Custom Integrated Circuits, May 1990, pp. 1-3.
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Eberhardt et al., "Design of Parallel Hardware Neural Network Systems from Custom Analog VLSI, `Building Block` Chips", IJCNN 1989 vol. 2, pp. II 14 183-II-190.

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