Static memory device provided with a signal generating circuit f

Details Static memory device provided with a signal generating circuit f Static memory device provided with a signal generating circuit f

1989-08-29

1991-07-02

Bowler, Alyssa H.

Static information storage and retrieval

Addressing

Sync/clocking

365203, 36518908, 36523003, G11C 700, G11C 800, G11C 11407

Patent

active

050291424

ABSTRACT:
An asynchronous type static memory device in which a plurality of pairs of bit lines are equalized upon change of address signals at a high speed is disclosed. The memory device comprises a plurality of memory blocks having a plurality of pairs of bit lines and a plurality of equalizing circuits provided for the plurality of pairs of bit lines, a plurality of address terminals receiving address signals, and an address transistion detecting circuit having a plurality of detection units, each of the detection units being coupled to one of the address terminals and generating a detecting signal when the signal at the associated address terminal coupled thereto is changed, a first logic section for generating a first number of intermediate logic signals for performing logical sum with respect to outputs of the detection units, the first number being smaller than the number of the detection units, and a plurality of second logic sections provided for the plurality of memory blocks respectively, each of the second logic sections operatively generating a control signal for enabling the equalizing circuits associated therewith as a result of performing a logical sum of the intermediate logic signals.

REFERENCES:
patent: 4751680 (1988-06-01), Wang et al.
patent: 4787068 (1988-11-01), Kihara
patent: 4843596 (1989-06-01), Miyatake et al.

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