Buffer memory control apparatus using address translation

Details Buffer memory control apparatus using address translation Buffer memory control apparatus using address translation

1988-09-29

1992-04-28

Chan, Eddie P.

Boots, shoes, and leggings

364239, 3642563, 364DIG1, G06F 1210, G06F 1300

Patent

active

051093359

ABSTRACT:
For address identification of a cache memory, a part of address bits of a logical address which are subject to address translation through a TLB and a part of address bits of the logical address which are not subject to address translation are applied in combination to an address array of the cache memory. Synonym generation is detected in response to buffer miss and synonym invalidation is executed in the buffer address array.

REFERENCES:
patent: 4056844 (1977-11-01), Izumi
patent: 4332010 (1982-05-01), Messina et al.
patent: 4618926 (1986-10-01), Kubo et al.
patent: 4683533 (1987-07-01), Shiozaki et al.
patent: 4943914 (1990-07-01), Kubo
European Search Report from European Patent Application No. EP 88 11 6184.
IBM Technical Disclosure Bulletin, vol. 22, No. 8A, Jan. 1980, pp. 3331-3333; J. M. Lee et al., "A Solution to the Synonym Problem".
IBM Technical Disclosure Bulletin, vol. 26, No. 12, May 1984, pp. 6264-6265; H. R. Brandt et al., "High Speed Buffer with Dual Directories".

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