Signal processing circuit for performing a pipelined matrix mult

Details Signal processing circuit for performing a pipelined matrix mult Signal processing circuit for performing a pipelined matrix mult

1990-05-11

1992-04-28

Boudreau, Leo H.

Facsimile and static presentation processing

Static presentation processing

Attribute control

358 80, H04N 146

Patent

active

051092735

ABSTRACT:
A signal processing circuit operates upon digitized signals from a plurality of linear color sensors that are spatially separated in the page scanning direction by a predetermined number of lines. The digitized signals are realigned in a line rephasing circuit, which provides sets of rephased color values for each scanned element of the original. A matrix multiplication is performed in a row sequential process upon the rephased signals by a group of multipliers, one multiplier for each row coefficient of the matrix. Each multiplier receives a rephased signal and a series of coefficients multiplexed into the circuit from a group of row coefficient registers. By clocking the rephased signals at a submultiple of the coefficient rate, a row-sequential matrix operation is serially performed in a pipelined manner.

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