Table cloth matrix of EPROM memory cells with buried junctions,

Details Table cloth matrix of EPROM memory cells with buried junctions, Table cloth matrix of EPROM memory cells with buried junctions,

1990-03-05

1991-07-02

Jackson, Jr., Jerome

357 235, H01L 2710, H01L 2715

Patent

active

050289799

ABSTRACT:
The table cloth matrix comprises a semiconductor substrate, wherein there are contained in deep layers, under strips of field oxide, source lines and drain lines parallel to one another, areas of floating gate connecting said source lines and drain lines and control gate lines, parallel to one another and perpendicular to said source lines and drain lines, in a condition superimposed over said floating gate areas. Each source line is alternated with two drain lines separated by an insulation zone, so that each drain line is associated with a single row of matrix cells.

REFERENCES:
patent: 4342099 (1982-07-01), Kuo
patent: 4376947 (1983-03-01), Chiu et al.
patent: 4451904 (1984-05-01), Sugiura et al.
patent: 4750024 (1988-06-01), Schreck
patent: 4868629 (1989-09-01), Eitan
patent: 4892840 (1990-01-01), Esquivel et al.

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