High speed CMOS flip-flop employing clocked tristate inverters

Details High speed CMOS flip-flop employing clocked tristate inverters High speed CMOS flip-flop employing clocked tristate inverters

1990-08-24

1992-08-18

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 3072721, 307480, 307481, H03K 326, H03K 1716

Patent

active

051401800

ABSTRACT:
A high speed, D-type flip-flop is implemented using eight complementary metal-oxide semiconductor (CMOS) tristate inverters. The flip-flop includes both D and D/ data input terminals and parallel data paths from the data input terminals to Q and Q/ output terminals. The improved circuit design realizes higher operating speed than prior CMOS flip-flops by eliminating the inverter delays present in single path flip-flops and providing only two gates in the data paths between the input and output terminals.

REFERENCES:
patent: 4463440 (1984-07-01), Nishiura et al.
patent: 4568842 (1986-02-01), Koike
patent: 4628217 (1986-12-01), Berndt
patent: 4691122 (1987-09-01), Schnizlein et al.
patent: 4777388 (1988-10-01), Widener
patent: 4785204 (1988-11-01), Terado et al.
patent: 4810908 (1989-03-01), Suzuki et al.
patent: 4932002 (1990-06-01), Houston
patent: 5017815 (1991-05-01), Shah et al.
patent: 5036217 (1991-07-01), Rollins et al.

Affiliated with

Also associated with

Rating

High speed CMOS flip-flop employing clocked tristate inverters does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed CMOS flip-flop employing clocked tristate inverters, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed CMOS flip-flop employing clocked tristate inverters will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1250699