Method of manufacturing a semiconductor device

Details Method of manufacturing a semiconductor device Method of manufacturing a semiconductor device

1989-09-26

1992-04-28

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 45, 437 46, 437 59, 437149, 437158, 148DIG31, 148DIG82, H01L 21265

Patent

active

051089440

ABSTRACT:
In a semiconductor device according to the present invention, a pair of element regions of a second conductivity type are formed so as to be electrically isolated from each other on a semiconductor substrate of a first conductivity type, a complementary MOS transistor is formed in one of the element regions of the second conductivity type, and a double-diffused MOS transistor is formed in the other element region of the second conductivity type. The complementary MOS transistor is of a surface channel type in which N- and P-channel MOS transistors are respectively formed in a pair of well diffusion layers of the first and second conductivity types formed in the element region of the second conductivity type, and conductivity types of the respective gate electrodes of the N- and P-channel MOS transistors are different from those of the respective well diffusion layers. The double-diffused MOS transistor is of a surface channel type in which a back gate region is formed so as to be self-aligned with the gate electrode and the conductivity type of the gate electrode is different from that of the well diffusion layer.

REFERENCES:
patent: 4214359 (1980-07-01), Kahng
patent: 4344081 (1982-08-01), Pao et al.
patent: 4403395 (1983-09-01), Curran
patent: 4626293 (1986-12-01), Schols
patent: 4757032 (1988-07-01), Contiero

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