Low power master-slave S/R flip-flop circuit

Details Low power master-slave S/R flip-flop circuit Low power master-slave S/R flip-flop circuit

1990-02-14

1991-07-02

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307291, H03K 3289, H03K 326

Patent

active

050288148

ABSTRACT:
A clocked S/R flip-flop having a master stage driving a slave stage. A logic signal at either a set or reset input of the maser stage charges one of a pair of capacitors respectively coupled to the outputs of a pair of FET devices respectively connected to such inputs and which are enabled during a clock pulse. The clock pulse also disables a pair of bipolar transistors respectively coupled to the outputs of the FET devices. The falling edge of the clock pulse enables the bipolar transistors, and the one which is connected to the charged capacitor produces a logic signal at the input of one of a pair of cross-coupled CMOS logic gates which constitute the slave stage. This produces a logic signal at the output of the slave stage corresponding to the binary value of the logic signal applied to the set or reset input of the master stage. The combination of bipolar and FET devices for coupling the master stage to the slave stage achieves high speed operation with minimum power consumption, and only a single series of clock pulses is required to establish clocked operation.

REFERENCES:
patent: 3624423 (1971-11-01), Borgini
patent: 3812384 (1974-05-01), Skorup
patent: 3812388 (1975-05-01), Southworth
patent: 3818251 (1974-06-01), Hoehn
patent: 4150392 (1979-04-01), Monaka
patent: 4300060 (1981-11-01), Yu
patent: 4656368 (1987-04-01), McCombs et al.
patent: 4680481 (1987-07-01), Landstedel et al.
IBM, Technical Disclosure Bulletin, vol. 20, No. 1, (1977), Race-Free Level Sensitive Master-Slave Latch Utilizing a Single Phase Clock, by D. E. Lee.

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