Fishing – trapping – and vermin destroying
Patent
1993-03-15
1994-06-14
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 35, 437 45, 437200, H01L 21266
Patent
active
053209745
ABSTRACT:
Insulating films formed on side walls of a gate electrode are removed for a self-alignment to selectively implant impurities only into end portions of a source region and a drain region. Therefore, p.sup.+ -type semiconductor regions are selectively formed only on sides near a channel region of the source and the drain regions. A punch through of the source or drain region is prevented by the p.sup.+ -type semiconductor regions controlling an inversion threshold voltage. Therefore, the impurity concentration of the p-type substrate can be settled low, and the semiconductor transistor device can be miniaturized without increasing a parasitic junction capacitance. Moreover, since the impurity concentration in the channel region is ununiform, a drivability of the transistor can be increased. As a result, a semiconductor transistor device with a high withstand voltage and a high drivability in which the inversion threshold voltage can be easily controlled, and a method for producing the same are provided.
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Hori Atsushi
Kameyama Shuichi
Segawa Mizuki
Shimomura Hiroshi
Chaudhari Chandra
Hearn Brian E.
Matsushita Electric - Industrial Co., Ltd.
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