Method for forming isolation region of semiconductor device

Details Method for forming isolation region of semiconductor device Method for forming isolation region of semiconductor device

1991-01-28

1992-08-18

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437947, 437981, 437 73, H01L 2176

Patent

active

051399644

ABSTRACT:
An improved LOCOS method for forming an isolation region with a higher breakdown voltage and a reduced width in a semiconductor device, comprising the steps of:

REFERENCES:
patent: 4965221 (1990-10-01), Dennison et al.
Martin, R., "Spacer for Improved Local Oxidation Profile", Xerox Disc. Bull. vol. 12, No. 5, Sep. 10, 1987.
Wolf, S., et al, Silicon Processing for the VLSI Era, vol. 1, p. 552, 1986.
Wolf, S., et al, Silicon Processing for the VLST Era, vol. 2, pp. 21-29 & 37, 1990.

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