Process of fabricating an MIS FET

Details Process of fabricating an MIS FET Process of fabricating an MIS FET

1989-05-05

1991-07-02

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 437192, 437200, 437931, 357 233, 148DIG105, 148DIG147, H01L 21265

Patent

active

050285548

ABSTRACT:
An LDD MIS FET comprises a silicide over the lightly doped regions to reduce the parasitic resistance and to prevent the depletion of the lightly-doped regions, reducing the hot carrier injection effect. By the provision of the silicide, the overall parasitic resistance can be made low. Moreover, the increase in the resistance of the lightly-doped region due to the negative charge being trapped at the interface of or in the oxide film over the lightly-doped region and the resultant degradation in the characteristic are eliminated.

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