Method of manufacturing a self-aligned bit line contact to a sem

Details Method of manufacturing a self-aligned bit line contact to a sem Method of manufacturing a self-aligned bit line contact to a sem

1994-12-27

1996-10-15

Thomas, Tom

Fishing, trapping, and vermin destroying

437 60, 437195, 437919, H01L 2170

Patent

active

055653723

ABSTRACT:
A method of manufacturing a semiconductor device. A conductive layer for the prevention of the capacitor coupling phenomenon is formed between a gate electrode and a bit line. A desired voltage is applied to the conductive layer. The capacitor coupling phenomenon between the bit line and the word line is eliminated as a result. Also, the contact size is reduced by forming a bit line contact with a self alignment method using the conductive layer and by forming a charge storage electrode contact with a self alignment method using the bit line and the conductive layer.

REFERENCES:
patent: 5114873 (1992-05-01), Kim et al.
patent: 5140389 (1992-08-01), Kimura et al.
patent: 5206183 (1993-04-01), Dennison
patent: 5229326 (1993-07-01), Dennison et al.
patent: 5270238 (1993-12-01), Kim
patent: 5352621 (1994-10-01), Kim
patent: 5362666 (1994-11-01), Dennison

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