Method for interconnecting a stack of integrated circuits at a v

Details Method for interconnecting a stack of integrated circuits at a v Method for interconnecting a stack of integrated circuits at a v

1991-03-15

1992-04-28

Arbes, Carl J.

Metal working

Method of mechanical manufacture

Electrical device making

29840, 361412, 437208, 437211, 437220, H05K 336

Patent

active

051075865

ABSTRACT:
Interconnected integrated cirucits (16) packaged at a very high density are fabricated beginning with a plurality of substrates (50 or 400 or 500) where each substrate has metal edge contact sites (12 or 507). Several substrates are joined together in a stack (82 or 402 or 512) held together tightly by bolts (62) or by a thermoplastic adhesive (510). An interconnect pattern (250 or 423) electrically connects integrated circuits (16) on different substrates. Defective substrates are removable from the stack for repair by removing the bolts or by heating the adhesive to soften it sufficiently to allow removal of the individual substrate. The interconnect pattern, which is removed whenever a substrate is replaced, is reapplied after the removed substrate has been replaced.

REFERENCES:
patent: 3029995 (1962-04-01), Doctor
patent: 3370203 (1968-02-01), Kravitz et al.
patent: 4283533 (1991-01-01), Go
patent: 4283755 (1981-08-01), Tracy
patent: 4574331 (1986-03-01), Smolley
patent: 4689103 (1987-08-01), Elarde
patent: 4714516 (1987-12-01), Eichelberger et al.
patent: 4733461 (1988-03-01), Nakano
patent: 4780177 (1988-10-01), Wojnarowski et al.
patent: 4783695 (1988-11-01), Eichelberger et al.
patent: 4811166 (1989-03-01), Alvarez et al.
patent: 4868712 (1989-09-01), Woodman
patent: 4882454 (1989-11-01), Peterson et al.
H. S. Cole et al., "Laser Processing for Interconnect Technology", Micro-Optoelectronic Materials, SPIE, vol. 877 (1988), pp. 92-96.
C. W. Eichelberger et al., "High-Density Interconnects for Electronic Packaging", Micro-Optoelectronic Materials, SPIE, vol. 877 (1988), pp. 90-91.

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