Variable-depth, self-regulating cache queue flushing system

Details Variable-depth, self-regulating cache queue flushing system Variable-depth, self-regulating cache queue flushing system

1996-01-29

1997-11-11

Lim, Krisna

395473, G06F 1300

Patent

active

056873484

ABSTRACT:
A FIFO invalidation queue for address words, from a spy module, are held for subsequent invalidation operations to a cache memory. The FIFO queue is programmably organized to indicate when it is almost full in which case it will switch to a priority operation which will give priority to invalidation cycles in the cache over the priority of the processor's cache access. When the FIFO queue indicates that it is almost empty, then the priority of the cache access by the processor is re-established as it was in normal conditions. The system operates concurrently in a self-regulating manner to load and unload addresses into the FIFO queue while also giving priority to flushing out the queue with invalidation cycles when preset upper limits are reached.

REFERENCES:
patent: 4195340 (1980-03-01), Joyce
patent: 4864543 (1989-09-01), Ward, Jr. et al.
patent: 5058006 (1991-10-01), Durdan et al.

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