Boots – shoes – and leggings
Patent
1995-08-04
1997-11-11
Lall, Parshotam S.
Boots, shoes, and leggings
39518311, 395464, 364DIG1, G06F 938
Patent
active
056873387
ABSTRACT:
A method and apparatus for instruction refetch in a processor is provided. To ensure that a macro instruction is available for refetching after the processor has handled an event or determined a correct restart address after a branch misprediction, an instruction memory includes an instruction cache for caching macro instructions to be fetched, and a victim cache for caching victims from the instruction cache. To ensure the availability of a macro instruction for refetching, the instruction memory (the instruction cache and victim cache together) always stores a macro instruction that may need to be refetched until the macro instruction is committed to architectural state. A marker micro instruction is inserted into the processor pipeline when an instruction cache line is victimized. The marker specifies an entry in the victim cache occupied by the victimized cache line. When the marker instruction is committed to architectural state, the victim cache entry specified by the marker is deallocated in the victim cache to permit storage of other instruction cache victims.
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Boggs Darrell D.
Colwell Robert P.
Fetterman Michael A.
Glew Andrew F.
Gupta Ashwani K.
Intel Corporation
Lall Parshotam S.
Vu Viet
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