Patent
1994-03-25
1996-05-07
Beausoliel, Jr., Robert W.
395280, G06F 1540
Patent
active
055155294
ABSTRACT:
In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, a first BPU transfers to cache storage only the even bits of a given data manipulation result, and a second BPU correspondingly transfers to cache storage only the odd bit information of the result. One BPU segregates the even bits of the result, adds parity information and sends the even bits and parity information to the cache unit. Similarly, the second BPU segregates the odd bits of the result, adds parity information and sends the odd bits and parity information to the cache unit. In the cache unit, the even and odd bit information are separately parity checked before storage into cache memory. If a parity error is observed in either set of information, an error signal is issued to institute appropriate remedial action.
REFERENCES:
patent: 4849979 (1989-07-01), Maccianti et al.
patent: 4953164 (1990-08-01), Asakura et al.
patent: 5019971 (1991-05-01), Lefsky et al.
patent: 5195101 (1993-03-01), Guenthner et al.
Boothroyd Donald C.
Lange Ronald E.
Shelly William A.
Beausoliel, Jr. Robert W.
Hua Ly V.
LandOfFree
Central processor with duplicate basic processing units employin does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Central processor with duplicate basic processing units employin, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Central processor with duplicate basic processing units employin will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1234852