Circuit arrangement for realizing logic elements that can be rep

Details Circuit arrangement for realizing logic elements that can be rep Circuit arrangement for realizing logic elements that can be rep

1997-12-04

1999-11-23

Ngo, Chuong Dinh

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708702, G06F 752, G06F 750

Patent

active

059917890

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

Logic elements are basic modules of today's digital computers. Since these basic modules are often used in digital computers, an improvement of a basic module has the direct effect of improving the entire apparatus in which this basic module is used. Above all, the number of transistors required for the realization of the basic module, the power loss that is converted in the basic module, and the speed of this basic module, are particularly important for the efficiency and the quality of such a basic module. The use of standardized technology is also an essential factor in assessing the quality of such a basic module.
The realization of logical basic circuits based on their functional equation by resistance logic (RTL), by diode transistor logic (DTL), by slow noise-proof logic (LSL) and by transistor-transistor logic (TTL), by emitter-coupled logic (ECL), complementary MOS logic (CMOS) and by NMOS logic (see U. Tietze, Ch. Shenk, Halbleiterschaltungstechnik, .sub.9 th ed., Springer-Verlag, 1990, ISBN 3-540-19475-4, pp. 201-219), is known. The use of neuron MOS transistors for the realization of a binary full adder is also known (T. Shibata, T. Ohini: "A functional 1405 transistor featuring gate-level weighted sum and threshold operations," IEEE Transactions on Electron Devices, 39, pages 1444-1455, 1992). The disadvantages of these known circuit arrangements, are above all, that a larger number of transistors is required in comparison to the invention specified below. The speed of known circuit arrangements is also considerably less than that of the circuit arrangement of the invention. A considerable disadvantage of neuron MOS transistors is that a specific technology (EEPROM or analog process) has to be used.
From (J. A. Hidalgo-Lopez et al., New Types of Digital Comparators, IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 29-32, April 1995), a comparator circuit is known that comprises two regeneratively coupled inverter stages and a reset unit. Two electrical quantities to be compared are supplied to the outputs of the inverter stages, at which the comparison result is also present. The source terminals of both inverter stages are connected with one another, and are connected to the frame via a clock transistor.
From (D. Ferrari and R. Stefanelli, Some New Schemes for Parallel Multipliers, Alta Frequenza, vol. 38, no. 11, pp. 843 to 852, XP 0020141008, 1969), a basic structure of a multiplier cell on the system plane is known with two different units for the formation of an output carry bit, as well as of an output summation bit. Fundamentally, the use of resistor-transistor logic (RTL) is proposed. The two elements are connected with one another in such a way that an output signal of a first element is fed back to an input of the second element. The fed-back output signal is weighted differently at the input of the second element, than are all other input signals.
Basic principles of a neuron 1405 inverter are known from (T. Shibata et al., Neuron-MOS Binary Logic Integrated Circuits--Part 2: simplifying Techniques of Circuit Configuration and a Practical Applications [sic], IEEE Transactions on Electron Devices, vol. 40, no. 6, pp. 974-979, 1993).


SUMMARY OF THE INVENTION

It is an object of the invention to realize logic elements whose function can be described by a threshold value equation, while avoiding the disadvantages of known circuit arrangements.
According to the circuit arrangement of the invention for realizing logic elements, a transistor unit has a plurality of transistors, the transistors being dimensioned such that cross-currents flowing through the transistors respectively represent a summand of a first term of the threshold value equation. A reference unit provides the second term of the threshold value equation. An evaluation unit compares the first term with the second term. All the transistors of the transistor unit are connected in parallel, and are connected via an output of the transistor unit with a first input of the e

REFERENCES:
patent: 3609329 (1971-09-01), Martin
patent: 3950636 (1976-04-01), Dao
patent: 4423339 (1983-12-01), Seelbach et al.
CMOS Inplementation And Fabrication Of The Pseudo Analog Neuron--Taheri--1993 IEEE--p. 266-270.
New Types of digital Comparators--Hidalgo-Lopez et al--Publication Date Apr. 30, 1995--p. 29-32.
A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations--Shibata et al--IEEE Transactions On Electron Devices, vol. 39, No. 6 Jun. 1992, p. 1444-1455.
Some New Schemes For Parallel Multipliers--Ferrari et al--100 Alta Frequenza--p. 843-851, Nov. 1969.
A New CMOS Neuron Circuit Based on a Cross-Coupled Current Comparator Structure--2334a IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences--E75-A (1992) Jul., No. 7, Tokyuo JP, p. 937-943.

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