Semiconductor integrated circuit with boundary scan circuit

Details Semiconductor integrated circuit with boundary scan circuit Semiconductor integrated circuit with boundary scan circuit

1994-11-04

1996-05-07

Canney, Vicent P.

39518303, G06F 1110

Patent

active

055155057

ABSTRACT:
A semiconductor integrated circuit has a boundary scan circuit in which the number of level converters is reduced while ensuring the freedom of device design. The semiconductor integrated circuit includes a logic circuit, a plurality of input and output pins having different logic levels, a plurality of serially connected testing circuits connected between the logic circuit and the input and output pins, and a plurality of level converters for converting logic levels. The serially connected testing circuits include a first group of testing circuits having the same logic levels as those of the input and output pins connected thereto, the testing circuits of the first group being connected directly in series to each other, and a second group of testing circuits having logic levels different from those of the input and output pins connected thereto. The testing circuits of the second group are connected through the level converters.

REFERENCES:
patent: 4645951 (1987-02-01), Uragami
patent: 5331219 (1994-07-01), Nakamura et al.
by Don Mc Clean et al., "Nikkei Electronics", No. 488, Dec. 11, 1989, pp. 314-320.
by Peter Hansen et al., "Nikkei Electronics", No. 490, Jan. 8, 1990, pp. 302-307.
by Stephen Evanczuk, "Nikkei Electronics", No. 492, Feb. 5, 1990, pp. 245-251.

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