Fixed slew rate bus driver circuit

Details Fixed slew rate bus driver circuit Fixed slew rate bus driver circuit

1984-01-16

1986-06-03

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307296R, 307299B, 307494, H03K 326, H03K 522

Patent

active

045932069

ABSTRACT:
A circuit for driving a serial data bus with serial logic data that is supplied to the circuit while buffering the logic data supplying circuit from the data bus. The circuit provides logic output pulses having controlled slew rates wherein the input logic data is not distorted but which inhibits undesired high frequency components associated with the fast rise and fall times of the leading and trailing edges of the input logic data pulses. The circuit comprises an inverting amplifier having capacitive feedback between the output and the inverting input of the amplifier, a buffer amplifier between the output of the inverting amplifier and the output of the circuit, and current switching circuitry for sinking and sourcing currents of equal magnitude at the input of the inverting amplifier depending on the relative magnitude of the input logic data pulses.

REFERENCES:
patent: 3348065 (1967-10-01), Schmidt
patent: 4122402 (1978-10-01), Main
patent: 4258330 (1981-03-01), Kaneka et al.

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