Implementation of binary floating point using hexadecimal floati

Details Implementation of binary floating point using hexadecimal floati Implementation of binary floating point using hexadecimal floati

1995-03-31

1997-11-11

Ngo, Chuong D.

Boots, shoes, and leggings

36471503, G06F 738, G06F 700

Patent

active

056871066

ABSTRACT:
A computer system supporting multiple floating point architectures. In an embodiment of the invention, a floating point unit (FPU) is optimized for hex format. The FPU uses a hex internal dataflow with a with an exponent and bias sufficient to support a binary floating point architecture. The FPU includes format conversion means, rounding means, sticky bit calculation means, and special number control means to execute binary floating point operations according to the IEEE 754 standard. An embodiment of the invention provides a system for executing floating point operations in either IBM S/390 hexadecimal format or IEEE 754 binary format.

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