Method and apparatus for minimizing asynchronous transmit FIFO u

Details Method and apparatus for minimizing asynchronous transmit FIFO u Method and apparatus for minimizing asynchronous transmit FIFO u

1998-02-13

1999-11-23

Marcelo, Melvin

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

370429, H04L 1200

Patent

active

059913045

ABSTRACT:
A circuit adapted to a first-in/first-out device ("FIFO") is disclosed. The circuit includes a counter and a first end of packet detector that is coupled to the counter. The first end of packet detector increments the counter if an end of packet is detected at an input of the FIFO. The circuit also includes a second end of packet detector coupled to the counter. The second end of packet detector decrements the counter if an end of packet is detected at an output of the FIFO. A detector circuit is coupled to an output of the counter and requests a bus transaction in response to the output of the counter. In another aspect, the present invention is a method of preventing data over-run errors in a receive FIFO having an input and an output. The method includes the steps of monitoring an input of the receive FIFO to determine a number of data packets received, monitoring an output of the receive FIFO for an end of packet to determine a number of data packets drained, and asserting a busy acknowledge line if the difference between the number of data packets received and the number of data packets drained is greater than and alternatively equal to a predetermined value.

REFERENCES:
patent: 4907225 (1990-03-01), Gulick et al.

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