Synchronous random access memory

Details Synchronous random access memory Synchronous random access memory

1998-03-19

1999-11-23

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 36523003, 36523005, 36523009, G11C 800

Patent

active

059912308

ABSTRACT:
In a synchronous random access memory, a data readout period, a data writein period, and a precharge period (or a reset period) are performed in order under the control of a control circuit 10, and the synchronous random access memory operates so that the executions of the data readout operation and the data writein operation are not overlapped under the control of the control circuit 10 comprising a sense amplifier activation generation circuit 11, a writein control signal generation circuit 12, and a reset signal generation circuit 13.

REFERENCES:
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patent: 5390149 (1995-02-01), Vogley et al.
patent: 5594704 (1997-01-01), Konishi et al.
patent: 5689473 (1997-11-01), Toda
patent: 5812488 (1998-09-01), Zagar et al.
patent: 5818793 (1998-10-01), Toda et al.
patent: 5867446 (1999-02-01), Konishi et al.
patent: 5872742 (1999-02-01), Kengeri et al.

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