Semiconductor memory device having built-in test circuits select

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395375, G01R 3128, G06F 1100

Patent

active

054674689

ABSTRACT:
A dynamic random access memory device internally carries out inspection sequences in a diagnostic mode of operation, and an instruction circuit incorporated therein discriminates a Write-CAS-Before-RAS entry cycle for simultaneously supplying test enable signals indicative of inspection sequences to internal test circuits, wherein the instruction circuit firstly decodes a multi-bit instruction signal and repeatedly produces a latch control signal for sequentially storing the decoded signal so that a plurality of test enable signal are simultaneously supplied to the test circuits.

REFERENCES:
patent: 5175840 (1992-12-01), Sawase et al.
patent: 5272673 (1993-12-01), Sugibayashi
patent: 5299163 (1994-03-01), Mortigami

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