Fishing – trapping – and vermin destroying
Patent
1995-03-15
1996-05-07
Fourson, George
Fishing, trapping, and vermin destroying
437100, H01L 21265, H01L 2120
Patent
active
055146040
ABSTRACT:
A MOSFET includes a first SiC semiconductor contact layer, a SiC semiconductor channel layer supported by the first SiC contact layer, and a second SiC semiconductor contact layer supported by the channel layer. The second contact and channel layers are patterned to form a plurality of gate region grooves therethrough. Each of the gate region grooves includes a base surface and side surfaces which are covered with groove oxide material. A plurality of metal gate layers are provided, each being supported in a respective one of the plurality of grooves. A plurality of deposited oxide layers are provided, each in a respective one of the grooves so as to be supported by a respective one of the plurality of metal gate layers. A first metal contact layer is applied to the surface of the first SiC contact layer, and a second metal contact layer is applied to a portion of the surface of the second SiC contact layer.
REFERENCES:
patent: 3047439 (1962-07-01), Van Daal et al.
patent: 4566172 (1986-01-01), Bencuya et al.
patent: 4641164, Dolny et al.
patent: 4761386 (1988-08-01), Buynoski
patent: 4767722 (1988-08-01), Blanchard
patent: 4903189 (1990-02-01), Ngo et al.
patent: 4908680 (1990-03-01), Matsuoka
patent: 4961100 (1990-10-01), Baliga
patent: 4962059 (1990-10-01), Nishioka et al.
patent: 4992390 (1991-02-01), Chang
patent: 5021845 (1991-06-01), Hashimoto
patent: 5086007 (1992-02-01), Ueno
patent: 5233215 (1993-08-01), Baliga
patent: 5242845 (1993-09-01), Baba et al.
patent: 5273910 (1993-12-01), Tran et al.
patent: 5323040 (1994-06-01), Baliga
Wolf, S. and R. Tauber, "Silicon Processing for the VLSI Era", Lattice Press Sunset Beach, Calif. 1986 pp. 182-183, vol. 1.
S. Wolf., "Silicon Processing for the VLSI Era", Lattice Press, Sunset Beach Calif., vol. 2 (1990).
"Plasma Etching Methods for the Formation of Planarized Tungsten Plugs Used in Multilevel VLSI Metallizations" by R. J. Saia, et al, Reprinted from Journal of the Electrochemical Society, vol. 135, No. 4, Apr. 1988, pp. 936-940.
"Selective CVD Tungsten Via Plugs for Multilevel Metallization", by D. M. Brown, et al, Reprinted from IEEE Electron Device Letters, vol. EDL-8, No. 2, Feb. 1987, pp. 55-57.
"Nitrogen-Implanted SiC Diodes Using High-Temperature Implantation", by Mario Ghezzo, et al, IEEE Electron Device Letters, vol. 13, No. 12, Dec. 1992.
Agosti Ann M.
Dutton Brian K.
Fourson George
General Electric Company
Snyder Marvin
LandOfFree
Vertical channel silicon carbide metal-oxide-semiconductor field does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Vertical channel silicon carbide metal-oxide-semiconductor field, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical channel silicon carbide metal-oxide-semiconductor field will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1226845