Apparatus and method for permitting reading of data from an exte

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364243, 36424341, 364239, 3642397, 364DIG1, 395250, 36518905, G11C 700, G06F 1202

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051796791

ABSTRACT:
A microprocessor is described which includes on a single substrate a central processing unit (CPU), write buffer and cache memory. The write buffer includes storage in each of its sections for a bit which indicates a hit/miss condition for the write cycle data stored in that section of the write buffer. If all these bits indicate that the new data in the write buffer has also been written into the cache memory, then read cycles are permitted before the data in the write buffer is written to external memory.

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IBM TDB, vol. 23, No. 1, Jun. 1980, Written by Blount et al., "Deferred Cache Storing Method" pp. 262-263.
Cenrier & Feautrier, A New Solution to Coherence Problems in Multicache Systems, IEEE Transactions on Computers, vol. C-27, No. 12, Sep. 1978, pp. 1112-1118.
"Cache Memories", by Alan Jay Smith, Computer Surveys, vol. 14, No. 3, Sep. 1982.

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