Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1994-12-12

1995-11-14

Fears, Terrell W.

Electricity: electrical systems and devices

Control circuits for electromagnetic devices

Systems for magnetizing, demagnetizing, or controlling the...

36518901, G11C 1122

Patent

active

054673020

ABSTRACT:
Bit lines BL0 and /BL0 are connected to a sense amplifier SA0, the gate of a first MOS transistor to a first word line WL0, a first electrode of a first ferrodielectric capacitor Cs1 to the source of the first Qn, the drain of the first Qn to BL0, a second electrode of Cs1 to a first plate electrode CP0, the gate of a second MOS transistor Qn to a second word line DWL0, a first electrode of a second ferrodielectric capacitor Cd2 to the source of the second Qn, the drain of the second Qn to /BL0, and a second electrode of Cd1 to a second plate electrode DCP0, and after turning off the second Qn, the logic voltage of DCP0 is inverted. Hence, in a semiconductor memory device employing the ferrodielectric element, the dummy memory capacitor is initialized securely, and high speed reading is enabled without concentration of power consumption.

REFERENCES:
patent: 5381364 (1995-01-01), Chern et al.

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