Divider and microcomputer including the same

Details Divider and microcomputer including the same Divider and microcomputer including the same

1994-03-07

1995-11-14

Mai, Tan V.

Boots, shoes, and leggings

3647462, G06F 752

Patent

active

054672996

ABSTRACT:
A subtraction-shift-type divider using a dividend or partial remainder represented by signed digits taking any of the values -1, 0, 1 and a divisor by twos complement representation. A selector, responding to values of a quotient digit at respective time points during the execution of division, converts the divisor into any of the same value, inverted value or "0" for outputting. An adder adds (subtracts) a partial remainder and 1 or 0. A quotient digit deciding circuit decides the next quotient digit from the quotient digits at respective time points during the execution of division, and a portion of the partial remainder obtained by the adder. The number of transistors constituting an actual circuit can be reduced by using a redundant signal digit (RSD) representation in the same way as the prior art and simplifying tables for deciding the quotient digit.

REFERENCES:
patent: 4878190 (1989-10-01), Darley et al.
patent: 5012439 (1991-04-01), Nash et al.
patent: 5132925 (1992-07-01), Kehl et al.
patent: 5153847 (1992-10-01), Takagi et al.
"A New Carry-Free Division Algorithm and Its Application to a Single-Chip 1024-b RSA Processor", IEEE Journal of Solid-State Circuits, vol. 25, No. 3, Jun. 1990, pp. 748-756.

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