Logic analyzer

Excavating

Patent

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Details

324 73R, 364900, G01R 3128, G09G 108

Patent

active

047138130

ABSTRACT:
A logic analyzer including at least a sampling system for sampling input data with a sampling clock signal comprises a condition decision circuit having inputs supplied with the input data and an internal clock signal for producing a conditioning signal in dependence on the input data in synchronism with the internal clock signal, a clock detection circuit for deciding whether the sampling clock signal makes appearance within a predetermined period of the internal clock signal to produce a signal representative of the result of the decision, and a control circuit having inputs supplied with the conditioning signal and the signal representative of said result for producing a trigger signal corresponding to the conditioning signal in dependence on the signal representative of the result of decision.

REFERENCES:
patent: 4364036 (1982-12-01), Shimizu
patent: 4375635 (1983-03-01), Leow et al.
patent: 4425643 (1984-01-01), Chapman et al.
patent: 4560981 (1985-12-01), Jackson et al.
patent: 4574354 (1986-03-01), Mihalik et al.
patent: 4585975 (1986-04-01), Wimmer

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