Logic circuit arrangement with field effect transistors matched

Details Logic circuit arrangement with field effect transistors matched Logic circuit arrangement with field effect transistors matched

1985-04-10

1987-12-15

Clawson, Jr., Joseph E.

357 239, 357 2312, 357 29, 357 54, H01L 2978

Patent

active

047136766

ABSTRACT:
A logic circuit arrangement has direct coupling of a drain and gate of two successive stages. At least one of the FET's has a buried electrode layer with adjacent, non-tunnelable insulator layers. The electrode layer is electrically charged from the outside by irradiation so that the zone comprising the length L.sub.g has a normally-off character.

REFERENCES:
patent: 4334347 (1982-06-01), Goldsmith et al.
patent: 4441036 (1984-04-01), Oldham
patent: 4467453 (1984-08-01), Chiu et al.
patent: 4521448 (1985-06-01), Sasaki
Siemens Forsch-u. Entwickl.-Ber., vol. 4, 1975, No. 6, pp. 345-351, "Erasable and Electrically Reprogrammable Read-Only Memory Using the N-Channel SIMOS One-Transistor Cell" by B. Rossler et al.

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