Linear feedback shift register for circuit design technology val

Electricity: measuring and testing – Plural – automatically sequential tests

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371 25, G01R 3128, G06F 1100

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047136057

ABSTRACT:
An apparatus and process employing an integrated circuit device technology within a linear feedback shift register using a cyclic redundancy check code scheme for validating the device technology under realistic very large scale integrated circuit operating conditions. By deploying two feedback shift registers in a full-duplex mode, the device technology can be subjected to arbitrarily-long, pseudo-random test signal sequences. Also, by checking the registers with variable-phase pulses, representative device delay time information can be obtained.

REFERENCES:
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Neil et al.; "Designing a . . . "; Electronics; Mar. 1, 1979; pp. 122-128.
Smith, J. E.; "Measures of the Effectiveness of Fault Signature Analysis"; IEEE Trans. on Computers; vol. C-29, No. 6; Jun. 1980; pp. 510-514.
Patel, A. M.; "A Multi-Channel CRC Register"; Proceedings of the Spring Joint Computer Conference, 1971; pp. 11-14.

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