Multiply-add unit and data processing apparatus using it

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3647151, G06F 738, G06F 700

Patent

active

058896902

ABSTRACT:
A multiply-add unit includes a digit alignment shift number and exponent generator unit, an addend digit alignment and sign adjusting unit, a multiplier array, a sticky-bit for addend lower digits generator unit, a leading digit detector unit, a carry propagate adder, an exponent normalizing unit, an addend higher digit incrementer, a sticky-bit generator unit, a normalizing shifter, a positive number conversion and rounder unit, and an exponent correction unit. The multiplier array is an array of carry save adders. The leading digit detector unit receives the two terms of carry and sum parts from the multiplier array, sequentially checks a digit pair of "0" to "1" at each corresponding digit position from the highest digit, and detects the leading non-zero digit of the absolute values depending upon what digit pair values are (11, 00, 10, 01) from higher to lower digit position.

REFERENCES:
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patent: 5329228 (1994-07-01), Burgess et al.
patent: 5373461 (1994-12-01), Bearden et al.
patent: 5471410 (1995-11-01), Bailey et al.
patent: 5493520 (1996-02-01), Schmookler et al.
Digest of Papers--1994 Spring Compcon, "The PowerPc 603 Microprocessor: A High Performance, Low Power, Superscalar RISC Microprocessor", B. Burgess et al, pp. 300-306.

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