Boots – shoes – and leggings
Patent
1998-04-17
1999-03-30
Teska, Kevin J.
Boots, shoes, and leggings
364488, 364489, 364490, 364491, G06F 1700
Patent
active
058896872
ABSTRACT:
The present invention provides a device simulation method comprising at least the steps of: inputting a geometry of a semiconductor device, a donor and an acceptor impurity concentrations at each point inside the semiconductor device and also terminal voltages of the semiconductor device (step S101); setting initial values by obtaining electron concentrations n, and n.sub.J and also hole concentrations p.sub.I and p.sub.J with respect to given points I and J respectively inside the semiconductor device and also a potential at each point (step S102); obtaining a voltage difference .PSI..sub.dd across a prescribed segment dd along a segment IJ connecting the points I and J (step S103); calculating an electron current density J.sub.eIJ of the segment IJ by an equation J.sub.eLJ =C.sub.eI .multidot.A(.PHI..sub.edd)-C.sub.eJ .multidot.A(-.PHI..sub.edd) using a constant C.sub.eI dependent on the electron concentration n.sub.J, a constant C.sub.eJ dependent on the electron concentration n.sub.J, and a voltage difference (.PHI..sub.edd =.PSI..sub.dd /NV.sub.e) across the segment dd normalized by an electron's thermal voltage (NV.sub.e =k.multidot.T.sub.e /(-q)) (step S104); calculating a hole current density J.sub.hIJ of the segment IJ by an equation J.sub.hIJ =C.sub.hI .multidot.A(.PHI..sub.hdd)-C.sub.hJ .multidot.A(-.PHI..sub.hdd) using a constant C.sub.hI dependent on the hole concentration p.sub.I, a constant C.sub.hJ dependent on the hole concentration p.sub.J, and a voltage difference ((.PHI..sub.hdd =.PSI..sub.dd /NV.sub.h) across the segment dd normalized by a hole's thermal voltage (NV.sub.h =k.multidot.T.sub.h /q) (step S105); and outputting a terminal current, where A(.PHI.)=1/(exp(.PHI.)+1). The present invention provides also a device simulator that can perform this device simulation method for fabricating semiconductor devices, and a storage medium storing the program to perform this device simulation method. The present invention further provides a device fabrication method employing the device simulation method.
REFERENCES:
patent: 5103415 (1992-04-01), Omura et al.
patent: 5627772 (1997-05-01), Sonoda et al.
patent: 5684723 (1997-11-01), Nakadai
Rorris et al., "A New Approach to the Simulation of the Coupled Point Defects and Impurity Diffusion" IEEE Transactions on Computer-Aided Design, pp. 1113-1112. Oct. 1990.
Klaassen, "A Unified mobility Model for Device Simulation", 1990 IEEE, pp. 14.3.1-14.3.4, Apr. 1990.
Siegfried Selberherr, "Analysis and Simulation of Semiconductor Devices", Chapter 4, The Physical Parameters, pp. 80-103.
Siegfried Selberherr, "Analysis and Simulation of Semiconductor Devices", Chapter 6, The Discretization of the Basic Semiconductor Equations, pp. 149-175.
Siegfried Selberherr, "Analysis and Simulation of Semiconductor Devices", Chapter 7, The Solution of Systems of Nonlinear Algebraic Equations, pp. 203-213.
Noritoshi Konishi, et al., "Development of Low Temperature Device Simulator Based on Universality Mobility Model", Technical Report of IEICE, SDM92-93, VLD92-68, 1992-10.
D.L. Scharfetter, et al., "Large-Signal Analysis of a Silicon Read Diode Oscillator", IEEE Transactions on Electron Devices, vol. ED-16, No. 1, pp. 64-77, Jan. 1969.
Woo-Sung Choi, et al., "A Time Dependent Hydrodynamic Device Simulator SNU-2D With New Discretion Scheme and Algorithm", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 13, No. 7, pp. 899-908, Jul. 1994.
Kabushiki Kaisha Toshiba
Roberts A. S.
Teska Kevin J.
LandOfFree
Simulator, simulation and fabrication methods of semiconductor d does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Simulator, simulation and fabrication methods of semiconductor d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Simulator, simulation and fabrication methods of semiconductor d will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1220440